1. Field of the Invention
The invention relates to an information recording and reproducing apparatus of a magnetic disk, an MO, an optical disk, a magnetic tape, or the like, an information recording and reproducing method, and a signal decoding circuit. More particularly, the invention relates to information recording and reproducing apparatus and method and a signal decoding circuit, for performing a timing recovery after a head reproduction signal is made discrete by an asynchronous clock.
2. Description of the Related Arts
In a conventional timing reproduction loop for a timing recovery of a read channel LSI, a sampling clock in an A/D converter and a symbol rate clock for making discrimination are the same. To obtain optimum discrimination timing, therefore, it is necessary for directly controlling a phase of the sampling clock of the A/D converter. Aside from it, there is also a method whereby the sampling clock of the A/D converter is fixed and the optimum discrimination timing is obtained by a signal interpolation for realizing a digital PLL. According to the signal interpolating method, in order to cope with a change in symbol rate due to a frequency offset, it is necessary to perform a sampling at a frequency higher than the symbol rate. Symbol discrimination is made after a sampling signal is equalized and subsequently the signal is converted into a sampling signal of the symbol rate by the signal interpolation. According to the discriminating method, in both of the above cases, a level of a read waveform equalized to a target of PR (Partial Response) is discriminated by a soft decision according to Viterbi or a hard decision according to a comparison with a reference.
FIG. 1 is a block diagram of a data reproducing unit having a timing recovery unit which is used in a conventional magnetic recording and reproducing apparatus. An analog voltage generated from a reproducing head is amplified by a preamplifier of a head IC and, thereafter, converted into a digital signal via a variable gain amplifier (VGA) 1200, a CT filter 1202 functioning as a low pass filter, and an A/D converter (ADC) 1204. Subsequently, waveform equalization is executed by an FIR filter 1206 and, thereafter, a decoding is performed by a Viterbi decoder 1208. The decoded data is further decoded by an RLL decoder 1210. In a timing recovery unit 1211, a PLL for controlling timing of a clock for sampling a head reproduction signal by the A/D converter 1204 is constructed by an error detector 1216, a loop filter 1218, and a voltage controlled oscillator (VCO) 1220. A gain controller 1212 is provided for the VGA 1200. The gain controller 1212 controls a gain and corrects an amplitude. That is, the timing recovery unit 1211 obtains a phase offset AT by using an output signal y of the FIR filter 1206 and a discrimination value y^ from the Viterbi decoder 1208 and controls an oscillating frequency of the VCO 1220 so as to eliminate the phase error Δτ. Thus, a feedback loop in which a sampling position of the A/D converter 1204 is controlled is formed. A gain error AG is obtained by using the output signal y of the FIR filter 1206 and its discrimination value y^. A control voltage Vg of the gain controller 1212 is adjusted so as to eliminate the gain error ΔG, thereby correcting the amplitude by the VGA 1200. Further, a phase offset detector 1214 is provided for the timing recovery unit 1211. In a head portion of a preamble 1223 for phase lead-in of reproduction data serving as an ADC output in FIG. 2A, the phase offset detector 1214 detects an initial phase error (phase offset) Δτ0 by a phase offset calculation 1226 in FIG. 2B, presets the initial phase error Δτ0 into the loop filter 1218, and executes a phase lead-in 1228 in FIG. 2C. According to the phase lead-in by the detection of the initial phase error, what is called a zero phase start is performed, thereby shortening a lead-in time in a subsequent frequency/phase lead-in 1230 using the preamble 1223.
FIG. 3 shows another example of a conventional data reproducing unit, and a timing recovery is performed by a phase loop of a digital PLL. In this case, a sampling is executed to the A/D converter 1204 asynchronously with a reproduction signal by using a fixed clock which is generated from a clock oscillator 1221. Subsequently to the FIR filter 1206, an FIR interpolating filter 1240 is provided. The FIR interpolating filter 1240 operates as a digital VCO by a combination with a digital accumulator 1222. The phase error Δτ obtained by the error detector 1216 of the timing recovery unit 1211 is integrated by the loop filter 1218 and further integrated by the digital accumulator 1222, and tap coefficients of the FIR interpolating filter 1240 are adjusted in accordance with the phase error Δτ, thereby matching the sampling rate by the fixed clock with the timing of the inherent symbol rate.
The phase offset detector 1214 is provided for the timing recovery unit 1211. The initial phase error (phase offset) Δτ0 of the phase is detected in the head portion of the preamble and preset into the digital accumulator 1222, thereby performing the phase lead-in of the zero phase start.
As mentioned above, in the conventional timing recovery unit, the initial phase error is detected in the head portion of the preamble and compensated, and the frequency lead-in is performed in the residual preamble. Compensation for the initial phase error of read-out data can be made. However, no consideration is given to a frequency offset, and it is difficult to obtain a wide frequency lead-in range. According to the conventional timing recovery unit, the lead-in is performed by a feedback control of the loop from a state where it has the frequency offset (initial frequency error). Therefore, in order to widen the frequency lead-in range further, a preamble which is long to a certain extent is necessary. There is a problem such that format efficiency of the magnetic recording and reproducing apparatus deteriorates.